1. Field of the Invention
The present invention relates to ceramic electronic components, and more specifically, it relates to a multi-layered ceramic electronic component including ceramic layers and internal electrodes to generate capacitance.
2. Description of the Related Art
In recent years, as electronic apparatuses, such as mobile phones and portable music players, are being downsized, electronic components to be mounted thereon have been downsized. For example, in multi-layered chip ceramic electronic components typified by multi-layered chip ceramic capacitors, in order to reduce the chip size while maintaining desired properties, the thickness of their ceramic layers has been reduced.
With the reduction in the thickness of the ceramic layers, there is a tendency to stack a greater number of thin ceramic layers. Usually, a multi-layered ceramic electronic component includes ceramic layers and internal electrodes that are alternately stacked. The internal electrodes do not completely cover the ceramic layers so as not to be exposed at side surfaces of the chip. The internal electrodes are arranged at inner locations of the ceramic layers and away from peripheries of the ceramic layers, thus causing differences in the level between the internal electrodes and the ceramic layers. An increase in the number of stacked ceramic layers is likely to cause structural defects, such as delamination, due to such level differences.
To overcome the foregoing problems, for example, a method for offsetting the level differences is disclosed in Japanese Unexamined Patent Application Publication No. 56-94719. The method includes printing an internal electrode pattern onto ceramic green sheets and then applying a ceramic paste to portions at which the internal electrode pattern is not printed.
In the method described above, the level differences between ceramic layers and internal electrodes are prevented. However, minute gaps are formed between ends of the internal electrodes and the ceramic layers during firing due to differences in shrinkage behavior during sintering between the internal electrodes and the ceramic layers. Then, water and moisture can penetrate into the gaps. Thus, the chip has poor resistance to moisture.
As a technique associated with Japanese Unexamined Patent Application Publication No. 56-94719 described above, a method is disclosed in Japanese Unexamined Patent Application Publication No. 2004-96010. According to the method, SiO2 is added to a ceramic paste for offsetting level differences so as to reduce the difference in shrinkage behavior during sintering between the ceramic and the internal electrodes.
Even in the method disclosed in Japanese Unexamined Patent Application Publication No. 2004-96010, however, it is very difficult to completely match the shrinkage behavior during sintering of the ceramic to that of the internal electrodes, and thus, this solution to the problem of poor moisture resistance due to the gaps is not satisfactory.
Portions offsetting the level differences are located near the outer surface of the chip. Thus, the ceramic paste applied to the portions is easily sintered because heat produced in a firing step is easily conducted to the portions. In the method disclosed in Japanese Unexamined Patent Application Publication No. 2004-96010, moreover, the addition of SiO2 to the ceramic paste leads to a further reduction in the sintering temperature. Thereby, gaps located near side surfaces are excessively sintered, which is likely to cause problems of structural defects and a reduction in the strength of the main body of a capacitor.
Furthermore, a method for solving the problem of level differences is disclosed in Japanese Unexamined Patent Application Publication No. 2005-101301. According to the method, Cu is added to a ceramic paste for offsetting level differences so that the Cu in the ceramic paste is alloyed with Ni in internal electrodes, thereby enhancing the bondability between the internal electrodes and level difference offsetting portions. In the method disclosed in Japanese Unexamined Patent Application Publication No. 2005-101301, however, the resulting alloy of Ni and Cu easily undergoes a redox reaction, depending on a firing atmosphere and other factors.
After volume expansion caused by an oxidation reaction occurs, volume reduction caused by a reduction reaction occurs, thus gaps in the level difference offsetting portions are formed. Thus, currently it is difficult to ensure sufficiently reliable moisture resistance for a multi-layered chip.